1. Field of Invention
The invention relates to an integration scheme for reducing the variation of the Top Trench Oxide (TTO) thickness caused by a zipper-like profile of opened-up voids in a poly trench fill in preparing vertical DRAM memory chips, where the thickness variation is in the same 30 nm range as the final target separation of the conducting, deep trench including buried strap and vertical gate array transistor. Reducing the TTO thickness variation to create a flatter surface improves the process control and reduces the required margins in the fabrication of semiconductor chips in regard to on/off currents and channel length control.
2. Description of the Related Art
DRAM memory chip area optimization normally entails incorporation of the transistor into the capacitor trench. These xe2x80x9cchipsxe2x80x9d, also known as electronic integrated circuits are formed by placement and interconnection of selected electronic devices, such as transistors, within a semiconductor substrate. The electronic devices are interconnected using an array of surface conductors carrying data signals through which the devices communicate.
With extensive use of storage device deep trench etches in silicon substrates, the trend in trench technology has moved the access transistor or vertical trench cell (VTC) from the top surface to the trench sidewall, thereby allowing a long channel device and avoiding the short channel effects that degrade trench retention time.
Further, the vertical trench cell (VTC) use of a collar etch/back followed by buried strap poly Si low pressure chemical vapor deposition (LPCVD) deposition and subsequent poly Si etch-back leaves the poly silicon in the recessed region where the collar oxide was etched away. This is done either for the complete collar or, in the case of single sided cell designs, only on one side of the collar (single sided strap). Thereafter, a Top Trench Oxide (TTO) is deposited by high-density plasma (HDP) to isolate the poly Si deep trench fill from poly gate conductor. The TTO thickness control is critical as it determines the channel length and contact from the xe2x80x98buried strapxe2x80x99(drain) to channel.
When poly Si is deposited into the deep trench by low-pressure chemical vapor deposition (LPCVD), it leaves a seam and voids along the seam in the deep trench, to create a zipper-like profile. During recessing the poly Si to define the top of the transition region between the capacitor and gate conductor (typically 350 nm below the Si surface) the voids and seam are opened in a way such that an undesirable topography is left in the deep trench. The recess is typically accomplished by a dry etch, such as chemical downstream etching (CDE).
The consequences of the zipper-like profile are: poor TTO thickness control; varying channel length; poor or no electrical contact for the deep trench to the transistor; and gate to capacitor leakage.
There are severe problems due to the effective TTO thickness variations within a wafer, from wafer to wafer, and from lot to lot during production of the microelectronic devices, such that device performance is extremely sensitive to these thickness variations. More specifically, the on/off currents and threshold voltage are especially effected by the channel length variationsxe2x80x94of which the root cause is attributable to the underlying TTO topography caused by varying shapes of deep trench (DT) poly zipper profile of opened-up voids in the poly trench film, and these opened-up voids are in the same range as the final target separation of trench and array transistor, of about 30 nm.
The invention process creates a flatter or more even surface of the top trench oxide (TTO) on which there is normally uneven topography caused by the zipper-like profile of opened-up-voids in the poly trench film. In general, the invention process of creating a flatter or more even surface TTO is accomplished through the use of high density plasma (HDP) polysilicon deposition, in which the deposited layers are formed by flowing SiH4 or SiH4 plus additional H2 in an inert ambient such as Ar or He to cause polysilicon films to be deposited. This poly Si layer serves additionally in the BS formation, thereby lending simplicity to the invention process.